Liquid crystal display and driving method thereof

ABSTRACT

A liquid crystal display for recognizing a flicker with the naked eyes in a step of inspecting a flicker in the case where a liquid crystal display is driven with a frame frequency of 120 Hz is disclosed. 
     In the liquid crystal display, a timing controller supplies a first frame inversion polarity signal which is used at a first frame inversion and, at the same time supplies a gate start pulse which indicates a supply of a scanning pulse. A frame polarity signal converting means converts a first frame inversion polarity signal into a second frame inversion polarity signal in response to the gate start pulse. And a data driver changes the inputted frame into a second frame inversion in response to the second frame inversion polarity signal.

This application claims the benefit of Korean Patent Application No.P2006-108856 filed in Korea on Nov. 6, 2006, which is herebyincorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid crystal display, and moreparticularly to a liquid crystal display that is adaptive forrecognizing a flicker with the naked eyes in a step of inspecting aflicker in the case where a liquid crystal display is driven with aframe frequency of 120 Hz, and a driving method thereof.

2. Description of the Related Art

Generally, a liquid crystal display controls light transmittance ofliquid crystal cells in accordance with video signals to thereby displaya picture. An active matrix type of liquid crystal display having aswitching device provided for each liquid crystal cell is advantageousfor an implementation of moving picture because it permits an activecontrol of the switching device. The switching device used for theactive matrix liquid crystal display mainly employs a thin filmtransistor (hereinafter, referred to as “TFT”) as shown in FIG. 1.

Referring to FIG. 1, the liquid crystal display of the active matrixtype converts a digital input data into an analog data voltage on thebasis of a gamma reference voltage to supply it to a data line DL and,at the same time supply a scanning pulse to a gate line GL, therebycharging a liquid crystal cell Clc.

A gate electrode of the TFT is connected to the gate line GL, a sourceelectrode is connected to the data line DL, and a drain electrode of theTFT is connected to a pixel electrode of the liquid crystal cell Clc andone end electrode of a storage capacitor Cst.

A common electrode of the liquid crystal cell Clc is supplied with acommon voltage Vcom.

When the TFT is turned-on, the storage capacitor Cst charges a datavoltage applied from the data line DL to constantly maintain a voltageof the liquid crystal cell Clc.

If the gate pulse is applied to the gate line GL, the TFT is turned-onto define a channel between the source electrode and the drainelectrode, thereby supplying a voltage on the data line DL to the pixelelectrode of the liquid crystal cell Clc. In this case, liquid crystalmolecules of the liquid crystal cell Clc are arranged by an electricfield between the pixel electrode and the common electrode to modulatean incident light.

A configuration of the related art liquid crystal display includingpixels which have such a structure is the same as shown in FIG. 2.

FIG. 2 is a block diagram showing a configuration of a liquid crystaldisplay of the related art.

Referring to FIG. 2, the liquid crystal display of the related artincludes a liquid crystal display panel 110, a data driver 120, a gatedriver 130, a gamma reference voltage generator 140, a backlightassembly 150, an inverter 160, a common voltage generator 170, a gatedriving voltage generator 180, and a timing controller 190. Herein, thedata driver 120 supplies a data to the data lines DL1 to DLm of theliquid crystal display panel 110. The gate driver 130 supplies ascanning pulse to the gate lines GL1 to GLn of the liquid crystaldisplay panel 110. The gamma reference voltage generator 140 generates agamma reference voltage to supply it to the data driver 120. Thebacklight assembly 150 irradiates a light onto the liquid crystaldisplay panel 110. The inverter 160 applies an AC current voltage and acurrent to the backlight assembly 150. The common voltage generator 170generates a common voltage Vcom to supply it to the common electrode ofthe liquid crystal cell Clc of the liquid crystal display panel 110. Thegate driving voltage generator 180 generates a gate high voltage VGH anda gate low voltage VGL to supply them to the gate driver 130. The timingcontroller 190 controls the data driver 120 and the gate driver 130.

The liquid crystal display panel 110 has a liquid crystal droppedbetween two glass substrates. On the lower glass substrate of the liquidcrystal display panel 110, the data lines DL1 to DLm and the gate linesGL1 to GLn perpendicularly cross each other. Each intersection betweenthe data lines DL1 to DLm and the gate lines GL1 to GLn is provided withthe TFT. The TFT supplies a data on the data lines DL1 to DLm to theliquid crystal cell Clc in response to the scanning pulse. The gateelectrode of the TFT is connected to the gate lines GL1 to GLn while thesource electrode thereof is connected to the data line DL1 to DLm.Further, the drain electrode of the TFT is connected to the pixelelectrode of the liquid crystal cell Clc and to the storage capacitorCst.

The TFT is turned-on in response to the scanning pulse applied, via thegate lines GL1 to GLn, to the gate terminal thereof. Upon turning-on ofthe TFT, a video data on the data lines DL1 to DLm is supplied to thepixel electrode of the liquid crystal cell Clc.

The data driver 120 supplies a data to the data lines DL1 to DLm inresponse to a data driving control signal DDC which is supplied from thetiming controller 190. Further, the data driver 120 converts digitalvideo data RGB which are supplied from the timing controller 190 into ananalog data voltage on the basis of a gamma reference voltage which issupplied from the gamma reference voltage generator 140 to supply it tothe data lines DL1 to DLm. Moreover, the data driver 120 changes aframe, which is inputted via the timing controller 190, in response to a1-frame inversion polarity signal 1FIV_POL which is supplied from thetiming controller 190, into a 1-frame inversion at the liquid crystaldisplay panel 110. Herein, the analog data voltage is realized as a grayscale at the liquid crystal cell Clc of the liquid crystal display panel110.

The gate driver 130 sequentially generates a scanning pulse in responseto a gate driving control signal GDC and a gate shift clock GSC whichare supplied from the timing controller 190 to supply them to the gatelines GL1 to GLn. In this case, the gate driver 130 determines a highlevel voltage and a low level voltage of the scanning pulse inaccordance with the gate high voltage VGH and the gate low voltage VGLwhich are supplied from the gate driving voltage generator 180.

The gamma reference voltage generator 140 receives a high-level powervoltage VDD to generate a positive gamma reference voltage and anegative gamma reference voltage to output them to the data driver 120.

The backlight assembly 150 is provided at the rear side of the liquidcrystal display panel 110, and is radiated by an AC voltage and acurrent which are supplied from the inverter 160 to irradiate a lightonto each pixel of the liquid crystal display panel 110.

The inverter 160 converts a square wave signal generated at the interiorthereof into a triangular wave signal, and then compares the triangularwave signal with a direct current power voltage VCC supplied from thesystem to generate a burst dimming signal proportional to the result. Ifthe burst dimming signal is generated, then a driving integrated circuitIC (not shown) controlling a generation of the AC voltage and a currentwithin the inverter 160 controls a generation of AC voltage and currentsupplied to the backlight assembly 150 in accordance with the burstdimming signal.

The common voltage generator 170 receives a high-level power voltage VDDto generate a common voltage Vcom, and supplies it to the commonelectrode of the liquid crystal cell Clc provided at each pixel of theliquid crystal display panel 110.

The gate driving voltage generator 180 is supplied with a high-levelpower voltage VDD to generate the gate high voltage VGH and the gate lowvoltage VGL, and supplies them to the gate driver 130. Herein, the gatedriving voltage generator 180 generates a gate high voltage VGH morethan a threshold voltage of the TFT provided at each pixel of the liquidcrystal display panel 110 and a gate low voltage VGL less then thethreshold voltage of the TFT. The gate high voltage VGH and the gate lowvoltage VGL generated in this manner are used for determining a highlevel voltage and a low level voltage of the scanning pulse generated bythe gate driver 130, respectively.

The timing controller 190 supplies digital video data RGB which aresupplied from a digital video card (not shown) to the data driver 120.Furthermore, the timing controller 190 generates a data driving controlsignal DCC and a gate driving control signal GDC usinghorizontal/vertical synchronization signals H and V in response to aclock signal CLK to supply them to the data driver 120 and the gatedriver 130, respectively. Herein, the data driving control signal DDCincludes a source shift clock SSC, a source start pulse SSP, a 1-frameinversion polarity signal 1FIV_POL, and a source output enable signalSOE, etc. The gate driving control signal GDC includes a gate startpulse GSP and a gate output enable signal GOE, etc.

Generally, a liquid crystal display 100 having such configurations isdriven with a frame frequency of 60 Hz. However, recently, a techniquewhich drives the liquid crystal display 100 with a frame frequency of120 Hz in order to improve a moving picture stain has been developed.

If the liquid crystal display 100 is driven with a frame frequency of 60Hz, since a flicker of 30 Hz is generated on a screen as shown in FIG.3A, the user can recognize a flicker with the naked eyes.

However, if the liquid crystal display 100 is driven with a framefrequency of 120 Hz, since a flicker of 60 Hz is generated on a screenas shown in FIG. 3B, the user cannot recognize a flicker with the nakedeyes.

In FIG. 3A and FIG. 3B, an AC voltage is defined such that an amount oflight which is irradiated from the front side of a panel is convertedinto an AC voltage. A DC voltage is defined such that an amount of lightwhich is irradiated from the front side of a panel is converted into aDC voltage.

In general, a process of inspecting and adjusting a flicker which isgenerated on a screen is carried out in the step of fabricating a liquidcrystal display. In this case, the inspector recognizes a flicker withthe naked eyes or using inspection equipment in the step of inspecting aflicker. Specially, a flicker of 30 Hz is generated in the case wherethe liquid crystal display is driven with a frame frequency of 60 Hz.Thus, the inspector recognizes a flicker with the naked eyes and adjustsa flicker. However, a flicker of 60 Hz which is not recognized by thenaked eyes is generated in the case where the liquid crystal display ofthe related art is driven with a frame frequency of 120 Hz. As a result,the inspector should recognize a flicker using separate inspectionequipment.

SUMMARY OF THE INVENTION

The present invention is to solve the above-mentioned problem.Accordingly, it is an object of the present invention to provide aliquid crystal display that is adaptive for converting a first frameinversion polarity signal into a second frame inversion polarity signal,and a driving method thereof.

It is another object of the present invention to provide a liquidcrystal display that is adaptive for converting a first frame inversionpolarity signal into a second frame inversion polarity signal to carryout a second frame inversion driving, and a driving method thereof.

It is still another object of the present invention to provide a liquidcrystal display that is adaptive for converting a first frame inversionpolarity signal into a second frame inversion polarity signal torecognize a flicker with the naked eyes in a step of inspecting aflicker in the case where a liquid crystal display is driven with aframe frequency of 120 Hz, and a driving method thereof.

It is still another object of the present invention to provide a liquidcrystal display that is adaptive for recognizing a flicker with thenaked eyes in a step of inspecting a flicker in the case where a liquidcrystal display is driven with a frame frequency of 120 Hz to reduce acost and time that are required for purchasing and using inspectionequipment, and a driving method thereof.

In order to achieve these and other objects of the invention, a liquidcrystal display according to the present invention comprises a timingcontroller that supplies a first frame inversion polarity signal whichis used at a first frame inversion and, supplies a gate start pulsewhich indicates a supply of a scanning pulse; a frame polarity signalconverting means that converts a first frame inversion polarity signalinto a second frame inversion polarity signal in response to the gatestart pulse; and a data driver that changes the inputted frame into asecond frame inversion in response to the second frame inversionpolarity signal.

The frame polarity signal converting means includes a first flip-flopthat generates a first period signal and a first inversed period signalin accordance with the gate start pulse; a second flip-flop thatgenerates a second period signal and a second inversed period signal inaccordance with the first period signal; and an exclusive OR gate thatcarries out an exclusive OR operation of the second period signal andthe first frame inversion polarity signal to generate the second frameinversion polarity signal.

The first flip-flop includes a clock terminal that receives the gatestart pulse, an output terminal that outputs the first period signal, aninversed output terminal that outputs the first inversed period signal,and an input terminal that is connected to the inversed output terminal.

In the liquid crystal display, a high level and a low level of the firstperiod signal and a first inversed period signal are maintained for aperiod of 120 Hz, respectively.

The second flip-flop includes a clock terminal that receives the firstperiod signal, an output terminal that outputs the second period signal,an inversed output terminal that outputs the second inversed periodsignal, and an input terminal that is connected to the inversed outputterminal.

In the liquid crystal display, a high level and a low level of thesecond period signal and a second inversed period signal are maintainedfor a period of 60 Hz, respectively.

In the liquid crystal display, the first frame inversion polarity signalis a 1 frame inversion polarity signal which is used at a 1-frameinversion.

In the liquid crystal display, the second frame inversion polaritysignal is a 2 frame inversion polarity signal that indicates a 2-frameinversion.

In the liquid crystal display, the second frame output terminal thatoutputs the first period signal, an inversed output terminal thatoutputs the first inversed period signal, and an input terminal that isconnected to the inversed output terminal.

A high level and a low level of the first period signal and a firstinversed period signal are maintained for a period of 120 Hz,respectively.

The second signal generating means is a flip-flop having a clockterminal that receives the first period signal, an output terminal thatoutputs the second period signal, an inversed output terminal thatoutputs the second inversed period signal, and an input terminal that isconnected to the inversed output terminal.

A high level and a low level of the second period signal and a secondinversed period signal are maintained for a period of 60 Hz,respectively.

The third signal generating means is an exclusive OR gate that carriesout an exclusive OR logic operation of the second period signal and thefirst frame inversion polarity signal to generate the second frameinversion inversion polarity signal is a 4 frame inversion polaritysignal that indicates a 4-frame inversion.

In the liquid crystal display, the second frame inversion polaritysignal is an N frame inversion polarity signal that indicates an N-frameinversion.

In the liquid crystal display, the second frame inversion polaritysignal is a Z frame inversion polarity signal that indicates a Z-frameinversion.

A liquid crystal display according to the present invention comprises afirst signal generating means that generates a first period signal and afirst inversed period signal in accordance with a gate start pulse; asecond signal generating means that generates a second period signal anda second inversed period signal in accordance with the first periodsignal; and a third signal generating means that generates a secondframe inversion polarity signal using the second period signal and thefirst frame inversion polarity signal.

The first signal generating means is a flip-flop having a clock terminalthat receives the gate start pulse, an polarity signal.

In the liquid crystal display, the first frame inversion polarity signalis a 1 frame inversion polarity signal which is used at a 1-frameinversion.

In the liquid crystal display, the second frame polarity signal is a 2frame inversion polarity signal that indicates a 2-frame inversion.

In the liquid crystal display, the second frame inversion polaritysignal is a 4 frame inversion polarity signal that indicates a 4-frameinversion.

In the liquid crystal display, the second frame inversion polaritysignal is an N frame inversion polarity signal that indicates an N-frameinversion. Wherein N is integer and is greater than 1.

In the liquid crystal display, the second frame inversion polaritysignal is a Z frame inversion polarity signal that indicates a Z-frameinversion. Wherein Z is integer and is greater than 2.

A method of driving a liquid crystal display according to the presentinvention comprises generating a first frame inversion polarity signalwhich is used at a first frame inversion and a gate start pulse thatindicates a supply of a scanning pulse; converting the first frameinversion polarity signal into a second frame inversion polarity signalin response to the gate start pulse; and changing the inputted frame toa second frame inversion in response to the second frame inversionpolarity signal.

The step of converting the first frame inversion polarity signal into asecond frame inversion polarity signal includes generating a firstperiod signal and a first inversed period signal in accordance with thegate start pulse; generating a second period signal and a secondinversed period signal in accordance with the first period signal; andcarrying out an exclusive OR logic operation of the second period signaland the first frame inversion polarity signal to generate the secondframe inversion polarity signal.

In the method, a high level and a low level of the first period signaland a first inversed period signal are maintained for a period of 120Hz, respectively.

In the method, a high level and a low level of the second period signaland a second inversed period signal are maintained for a period of 60Hz, respectively.

In the method, the first frame inversion polarity signal is a 1 frameinversion polarity signal which is used at a 1-frame inversion.

In the method, the second frame inversion polarity signal is a 2 frameinversion polarity signal that indicates a 2-frame inversion.

In the method, the second frame inversion polarity signal is a 4 frameinversion polarity signal that indicates a 4-frame inversion.

In the method, the second frame inversion polarity signal is an N frameinversion polarity signal that indicates an N-frame inversion.

In the method, the second frame inversion polarity signal is a Z frameinversion polarity signal that indicates a Z-frame inversion.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects of the invention will be apparent from thefollowing detailed description of the embodiments of the presentinvention with reference to the accompanying drawings, in which:

FIG. 1 is an equivalent circuit diagram showing a pixel provided at aliquid crystal display of a related art;

FIG. 2 is a block diagram showing a configuration of the liquid crystaldisplay of related art;

FIG. 3A is a diagram showing a characteristics of a flicker which isgenerated at a liquid crystal display driven with a frame frequency of60 Hz;

FIG. 3B is a diagram showing a characteristics of a flicker which isgenerated at a liquid crystal display driven with a frame frequency of120 Hz;

FIG. 4 is a block diagram showing a configuration of a liquid crystaldisplay according to an embodiment of the present invention;

FIG. 5 is a diagram showing an example of a characteristics of a 2-frameinversion of the liquid crystal display according to the embodiment ofthe present invention;

FIG. 6 is a circuit diagram of the frame polarity signal converter inFIG. 4;

FIG. 7 is a diagram showing a characteristics of a signal of the liquidcrystal display according to the embodiment of the present invention;

FIG. 8 is a flow chart showing a method of driving the liquid crystaldisplay according to the embodiment of the present invention; and

FIG. 9 is a flow chart showing in detail a step of generating the periodsignal and the 2 frame inversion polarity signal in FIG. 8.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Hereinafter, the preferred embodiments of the present invention will bedescribed in detail with reference to the accompanying drawings.

FIG. 4 is a block diagram showing a configuration of a liquid crystaldisplay according to an embodiment of the present invention. Herein, aliquid crystal display 200 of the present invention includes the gammareference voltage generator 140, the backlight assembly 150, theinverter 160, the common voltage generator 170, and the gate drivingvoltage generator 180 similar to the liquid crystal display 100 in FIG.2. However, for the sake of explanation, such configurations will beomitted in FIG. 4.

Referring to FIG. 4, the liquid crystal display 200 of the presentinvention includes the liquid crystal display panel 110, the gate driver130, a timing controller 210, a frame polarity signal converter 220, anda data driver 230. Herein, the timing controller 210 supplies a 1 frameinversion polarity signal 1FIV_POL which is used for a 1-frame inversionand, at the same time supplies a gate start pulse GSP that indicates asupply of a scanning pulse. The frame polarity signal converter 220converts a 1 frame inversion polarity signal 1FIV_POL from the timingcontroller 210 into a 2 frame inversion polarity signal 2FIV_POL inresponse to a gate start pulse GSP from the timing controller 210. Thedata driver 230 changes a frame, which is supplied from the timingcontroller 210, into a 2-frame inversion at the liquid crystal displaypanel 110 in response to a 2 frame inversion polarity signal 2FIV_POL,which is converted by the frame polarity signal converter 220.

The timing controller 210 supplies digital video data RGB which aresupplied from a system to the data driver 120. Furthermore, the timingcontroller 210 generates a data driving control signal DCC and a gatedriving control signal GDC using horizontal/vertical synchronizationsignals H and V in response to a clock signal CLK from a system tosupply them to the data driver 230 and the gate driver 130,respectively. Herein, the data driving control signal DDC includes asource shift clock SSC, a source start pulse SSP, and a source outputenable signal SOE, etc. The gate driving control signal GDC includes agate start pulse GSP and a gate output enable signal GOE, etc.

The timing controller 210 supplies a 1 frame inversion polarity signal1FIV_POL that indicates an inversion driving of a frame to the framepolarity signal converter 220, and supplies a gate start pulse GSP whichis used for converting a 1 frame inversion polarity signal 1FIV_POL tothe frame polarity signal converter 220.

The frame polarity signal converter 220 generates a first period signalPS1 in accordance with a gate start pulse GSP from the timing controller210, and then generates a second period signal PS2 in accordance withthe first period signal PS1. Furthermore, the frame polarity signalconverter 220 carries out an exclusive OR logic operation of thegenerated second period signal PS2 and a 1 frame inversion polaritysignal 1FIV_POL from the timing controller 210 to generate a 2 frameinversion polarity signal 2FIV_POL. In this case, the frame polaritysignal converter 220 supplies a 2 frame inversion polarity signal2FIV_POL to the data driver 230.

The data driver 230 supplies a data to the data lines DL1 to DLm inresponse to a data driving control signal DDC supplied from the timingcontroller 210. The data driver 230 converts digital video data RGBwhich are supplied from the timing controller 210 into an analog datavoltage on the basis of a gamma reference voltage to supply it to thedata lines DL1 to DLm. Furthermore, the data driver 230 is a frame,which is inputted via the timing controller 210, into a 2-frameinversion at the liquid crystal display panel 110 in response to a 2frame inversion polarity signal 2FIV_POL, which is supplied from theframe polarity signal converter 220. Herein, the analog data voltage isrealized as a gray scale at the liquid crystal cell Clc of the liquidcrystal display panel 110.

In this way, if the liquid crystal display 200 is driven with a 2-frameinversion, a polarity is inversed in a 2 frames unit as shown in FIG. 5.Thus, a flicker of 60 Hz which is generated at the liquid crystaldisplay 200 driven with a frame frequency of 120 Hz is converted into aflicker of 30 Hz in FIG. 3A. Accordingly, the inspector recognizes aflicker of 30 Hz which is generated on the liquid crystal display 220driven with a frame frequency of 120 Hz with the naked eyes to adjust aflicker in the step of inspecting a flicker.

On the other hand, since a technique of the present invention thatconverts a 1-frame inversion driving into a 2-frame inversion driving isused at a process of fabricating a product, the frame polarity signalconverter 220 is turned-on/off by an on/off switches thereof (notshown). In other words, in the step of inspecting and adjusting aflicker, the user operates the on/off switches to turn-on the framepolarity signal converter 220, thereby allowing a 2 frame inversionpolarity signal 2FIV_POL which is converted by the frame polarity signalconverter 220 to be supplied to the data driver 230. On the contrary, ifthe viewer uses the completed product, the frame polarity signalconverter 220 is maintained as an off-state to allow a 1 frame inversionpolarity signal 1FIV_POL which is generated by the timing controller 210to be supplied to the data driver 230.

FIG. 6 is a circuit diagram of the frame polarity signal converter inFIG. 4.

Referring to FIG. 6, the frame polarity signal converter 220 includes afirst flip-flop 221, a second flip-flop 222, and an exclusive OR gateXOR GATE 223. Herein, the first flip-flop 221 generates a first periodsignal PS1 in accordance with a gate start pulse GSP from the timingcontroller 210. The second flip-flop 222 generates a second periodsignal PS2 in accordance with a first period signal PS1 of the firstflip-flop 221. The exclusive OR gate 223 carries out an exclusive ORlogic operation of a second period signal PS2 which is generated by thesecond flip-flop 222 and a 1 frame inversion polarity signal 1FIV_POLfrom the timing controller 210 to generate a 2 frame inversion polaritysignal 2FIV_POL.

The first flip-flop 221 includes a clock terminal that receives the gatestart pulse GSP, an output terminal Q that outputs a first period signalPS1, an inversed output terminal /Q that outputs a first inversed periodsignal /PS1, and an input terminal D that is connected to the inversedoutput terminal /Q. Herein, a function of the first flip-flop 221 willbe described with reference to FIG. 7 as follows.

Referring to FIG. 7, if a gate start pulse GSP having a period of 120 Hzis inputted to a clock terminal of the first flip-flop 221, the firstflip-flop 221 outputs a first period signal PS1 of low level via anoutput terminal Q and, at the same time outputs a first inversed periodsignal /PS1 of high level via an inversed output terminal /Q for a 1period of a gate start pulse GSP. Sequentially, the first flip-flop 221outputs a first period signal PS1 of high level via an output terminal Qand, at the same time outputs a first inversed period signal /PS1 of lowlevel via an inversed output terminal /Q for the next 1 period. Thefirst flip-flop 221 outputs a first period signal PS1 and a firstinversed period signal /PS1 of which a high level and a low level arealternatively changed whenever a period of a gate start pulse GSP ischanged through a series of process of generating a signal.

Herein, a first period signal PS1 which is outputted via an outputterminal Q of the first flip-flop 221 is inputted to a clock terminal ofthe second flip-flop 222. A first inversed period signal /PS1 which isoutputted via an inversed output terminal /Q of the first flip-flop 221is inputted to an input terminal D of the first flip-flop 221.Furthermore, a high level and a low level of a first period signal PS1and a first inversed period signal /PS1 are maintained for a period of120 Hz, and then are converted into another level, respectively.

The second flip-flop 222 includes a clock terminal that receives a firstperiod signal PS1, an output terminal Q that outputs a second periodsignal PS2, an inversed output terminal /Q that outputs a secondinversed period signal /PS2, and an input terminal D that is connectedto an inversed output terminal /Q. Herein, a function of the firstflip-flop 222 will be described with reference to FIG. 7 as follows.

Referring to FIG. 7, if a first period signal PS1 which is maintained asa high level or a low level for a period of 120 Hz is inputted to aclock terminal of the second flip-flop 222, the second flip-flop 222outputs a second period signal PS2 of high level via an output terminalQ and, at the same time outputs a second inversed period signal /PS2 oflow level via an inversed output terminal /Q during a low level and ahigh level of a first period signal PS1 is sequentially inputted. Next,the second flip-flop 222 outputs a second period signal PS2 of low levelvia an output terminal Q and, at the same time outputs a second inversedperiod signal /PS2 of high level via an inversed output terminal /Q fora low level interval and a high level interval of the next first periodsignal PS1. The first flip-flop 222 outputs a second period signal PS2and a second inversed period signal /PS2 of which a high level and a lowlevel are alternatively changed whenever a sequential low level and asequential high level of a first period signal PS1 are changed through aseries of process of generating a signal.

Herein, a second period signal PS2 which is outputted via an outputterminal Q of the second flip-flop 222 is inputted to an input terminalof the exclusive OR gate 223. A second inversed period signal /PS2 whichis outputted via an inversed output terminal /Q of the second flip-flop222 is inputted to an input terminal D of the second flip-flop 222.Furthermore, a high level and a low level of a second period signal PS2and a second inversed period signal /PS2 are maintained for a period of60 Hz, and then are converted into another level, respectively.

The exclusive OR gate 223 includes a first input terminal which isconnected to an output terminal Q of the second flip-flop 222, a secondinput terminal which is connected to an output terminal of a 1 frameinversion polarity signal 1FIV_POL of the timing controller 210, and anoutput terminal which is connected to the data driver 230. Herein, afunction of the exclusive OR gate 223 will be described with referenceto FIG. 7 as follows.

Referring to FIG. 7, the exclusive OR gate 223 carries out an exclusiveOR logic operation of a second period signal PS2 which is inputted fromthe second flip-flop 222 and a 1 frame inversion polarity signal1FIV_POL from the timing controller 210 to generate a 2 frame inversionpolarity signal 2FIV_POL. More specifically, if a high level of a secondperiod signal PS2 and a 1 frame inversion polarity signal 1FIV_POL ofpositive polarity, or a low level of a second period signal PS2 and a 1frame inversion polarity signal 1FIV_POL of negative polarity issimultaneously inputted, the exclusive OR gate 223 outputs a 2 frameinversion polarity signal 2FIV_POL of negative polarity via an outputterminal. On the contrary, if a low level of a second period signal PS2and a 1 frame inversion polarity signal 1FIV_POL of positive polarity,or a high level of a second period signal PS2 and a 1 frame inversionpolarity signal 1FIV_POL of negative polarity is simultaneouslyinputted, the exclusive OR gate 223 outputs a 2 frame inversion polaritysignal 2FIV_POL of positive polarity via an output terminal.Furthermore, if a high level of a second period signal PS2 and a 1 frameinversion polarity signal 1FIV_POL of negative polarity, or a low levelof a second period signal PS2 and a 1 frame inversion polarity signal1FIV_POL of positive polarity is simultaneously inputted, the exclusiveOR gate 223 outputs a 2 frame inversion polarity signal 2FIV_POL ofpositive polarity via an output terminal.

A 1 frame inversion polarity signal 1FIV_POL is alternatively convertedat a rising edge that each period of a gate start pulse GSP is startedowing to an operating characteristics of the exclusive OR gate 223. Onthe contrary, a 2 frame inversion polarity signal 2FIV_POL which isoutputted from the exclusive OR gate 223 is continuously twicemaintained as a positive polarity or a negative polarity, and then apolarity thereof is inversed at a rising edge that each period of a gatestart pulse GSP is started. In other words, the exclusive OR gate 223continuously twice outputs a 2 frame inversion polarity signal 2FIV_POLof positive polarity, and then continuously twice outputs a 2 frameinversion polarity signal 2FIV_POL of negative polarity on the basis ofa rising edge part of each period of a gate start pulse GSP.Accordingly, the data driver 230 changes a frame, which is inputted fromthe timing controller 210, into a 2-frame inversion at the liquidcrystal display panel 110 in response to a 2 frame inversion polaritysignal 2FIV_POL from the exclusive OR gate 223 as shown in FIG. 5.

FIG. 8 is a flow chart showing a method of driving the liquid crystaldisplay according to the embodiment of the present invention.

Referring to FIG. 8, if a frame is inputted from a system (S810), thetiming controller 210 supplies a 1 frame inversion polarity signal1FIV_POL that indicates an inversion driving of a frame to the framepolarity signal converter 220 and, at the same time supplies a gatestart pulse GSP which is used for converting a 1 frame inversionpolarity signal 1FIV_POL to the frame polarity signal converter 220(S820).

Next, the frame polarity signal converter 220 generates a first periodsignal PS1 in accordance with a gate start pulse GSP from the timingcontroller 210, and then generates a second period signal PS2 inaccordance with the first period signal PS1 (S830). Furthermore, theframe polarity signal converter 220 carries out an exclusive OR logicoperation of the generated second period signal PS2 and a 1 frameinversion polarity signal 1FIV_POL from the timing controller 210 togenerate a 2 frame inversion polarity signal 2FIV_POL, thereby supplyingit to the data driver 230 (S840).

The data driver 230 changes a frame, which is inputted via the timingcontroller 210, into a 2-frame inversion to realize it at the liquidcrystal display panel 110 in response to a 2 frame inversion polaritysignal 2FIV_POL (S850).

FIG. 9 is a flow chart showing in detail a step of generating the periodsignal and the 2 frame inversion polarity signal in FIG. 8.

Referring to FIG. 9, if a gate start pulse GSP having a period of 120 Hzis inputted to a clock terminal of the first flip-flop 221 (S831), thefirst flip-flop 221 outputs a first period signal PS1 of low level viaan output terminal Q and, at the same time outputs a first inversedperiod signal /PS1 of high level via an inversed output terminal /Q fora 1 period of a gate start pulse GSP (S832). Sequentially, the firstflip-flop 221 outputs a first period signal PS1 of high level via anoutput terminal Q and, at the same time outputs a first inversed periodsignal /PS1 of low level via an inversed output terminal /Q for the next1 period (S833). In this case, a first period signal PS1 which isoutputted via an output terminal Q of the first flip-flop 221 isinputted to a clock terminal of the second flip-flop 222, and a firstinversed period signal /PS1 which is outputted via an inversed outputterminal /Q of the first flip-flop 221 is inputted to an input terminalD of the first flip-flop 221. Furthermore, a high level and a low levelof a first period signal PS1 and a first inversed period signal /PS1 aremaintained for a period of 120 Hz, and then are converted into anotherlevel, respectively.

If a first period signal PS1 which is maintained as a high level and alow level for a period of 120 Hz is inputted to a clock terminal of thesecond flip-flop 222 (S834), the second flip-flop 222 outputs a secondperiod signal PS2 of high level via an output terminal Q and, at thesame time outputs a second inversed period signal /PS2 of low level viaan inversed output terminal /Q during a low level and a high level of afirst period signal PS1 is sequentially inputted (S835). Next, thesecond flip-flop 222 outputs a second period signal PS2 of low level viaan output terminal Q and, at the same time outputs a second inversedperiod signal /PS2 of high level via an inversed output terminal /Q fora low level interval and a high level interval of the next first periodsignal PS1 (S836). In this case, a second period signal PS2 which isoutputted via an output terminal Q of the second flip-flop 222 isinputted to an input terminal of the exclusive OR gate 223. A secondinversed period signal /PS2 which is outputted via an inversed outputterminal /Q of the second flip-flop 222 is inputted to an input terminalD of the second flip-flop 222. Furthermore, a high level and a low levelof a second period signal PS2 and a second inversed period signal /PS2are maintained for a period of 60 Hz, and then are converted intoanother level, respectively.

Next, the exclusive OR gate 223 carries out an exclusive OR logicoperation of a second period signal PS2 which is inputted from thesecond flip-flop 222 and a 1 frame inversion polarity signal 1FIV_POLwhich is inputted from the timing controller 210 to generate a 2 frameinversion polarity signal 2FIV_POL (S837). In this case, if a high levelof a second period signal PS2 and a 1 frame inversion polarity signal1FIV_POL of positive polarity, or a low level of a second period signalPS2 and a 1 frame inversion polarity signal 1FIV_POL of negativepolarity is simultaneously inputted, the exclusive OR gate 223 outputs a2 frame inversion polarity signal 2FIV_POL of negative polarity via anoutput terminal. On the contrary, if a low level of a second periodsignal PS2 and a 1 frame inversion polarity signal 1FIV_POL of positivepolarity, or a high level of a second period signal PS2 and a 1 frameinversion polarity signal 1FIV_POL of negative polarity issimultaneously inputted, the exclusive OR gate 223 outputs a 2 frameinversion polarity signal 2FIV_POL of positive polarity via an outputterminal. Furthermore, if a high level of a second period signal PS2 anda 1 frame inversion polarity signal 1FIV_POL of negative polarity, or alow level of a second period signal PS2 and a 1 frame inversion polaritysignal 1FIV_POL of positive polarity is simultaneously inputted, theexclusive OR gate 223 outputs a 2 frame inversion polarity signal2FIV_POL of positive polarity via an output terminal.

As described above, the present invention is only an example of a casethat the liquid crystal display is driven by a 2-frame inversion method.Furthermore, the spirit of the present invention is not limited to this.

For example, if the spirit of the present invention is applied to aliquid crystal display which is driven by a 4-frame inversion method,the exclusive OR gate 223 is realized to generate a 4 frame inversionpolarity signal that indicates a 4-frame inversion. In this case,another signal instead of a 1 frame inversion polarity signal 1FIV_POLmay be used for generating a 4 frame inversion polarity signal.

For example, if the spirit of the present invention is applied to aliquid crystal display which is driven by an N-frame inversion method,the exclusive OR gate 223 is realized to generate an N frame inversionpolarity signal that indicates an N-frame inversion. In this case,another signal instead of a 1 frame inversion polarity signal 1FIV_POLmay be used for generating an N frame inversion polarity signal.

For example, if the spirit of the present invention is applied to aliquid crystal display which is driven by a Z-frame inversion method,the exclusive OR gate 223 is realized to generate a Z frame inversionpolarity signal that indicates a Z-frame inversion. In this case,another signal instead of a 1 frame inversion polarity signal 1FIV_POLmay be used for generating a Z frame inversion polarity signal.

As described above, the present invention converts a first frameinversion polarity signal into a second frame inversion polarity signalto carry out a second frame inversion driving. Thus, the presentinvention converts a flicker of 60 Hz which is generated when a liquidcrystal display is driven with a frame frequency of 120 Hz into aflicker of 30 Hz. As a result, the present invention recognizes aflicker with the naked eyes in a step of inspecting a flicker in thecase where a liquid crystal display is driven with a frame frequency of120 Hz to reduce a cost and time that are required for purchasing andusing inspection equipment.

Although the present invention has been explained by the embodimentsshown in the drawings described above, it should be understood to theordinary skilled person in the art that the invention is not limited tothe embodiments, but rather that various changes or modificationsthereof are possible without departing from the spirit of the invention.Accordingly, the scope of the invention shall be determined only by theappended claims and their equivalents.

1. A liquid crystal display, comprising: a timing controller thatsupplies a first frame inversion polarity signal which is used at afirst frame inversion and, supplies a gate start pulse which indicates asupply of a scanning pulse; a frame polarity signal converting meansthat converts a first frame inversion polarity signal into a secondframe inversion polarity signal in response to the gate start pulse; anda data driver that changes the inputted frame into a second frameinversion in response to the second frame inversion polarity signal. 2.The liquid crystal display according to claim 1, wherein the framepolarity signal converting means includes: a first flip-flop thatgenerates a first period signal and a first inversed period signal inaccordance with the gate start pulse; a second flip-flop that generatesa second period signal and a second inversed period signal in accordancewith the first period signal; and an exclusive OR gate that carries outan exclusive OR logic operation of the second period signal and thefirst frame inversion polarity signal to generate the second frameinversion polarity signal.
 3. The liquid crystal display according toclaim 2, wherein the first flip-flop includes a clock terminal thatreceives the gate start pulse, an output terminal that outputs the firstperiod signal, an inversed output terminal that outputs the firstinversed period signal, and an input terminal that is connected to theinversed output terminal.
 4. The liquid crystal display according toclaim 3, wherein a high level and a low level of the first period signalare maintained for a period of 120 Hz, respectively, and wherein a highlevel and a low level of the a first inversed period signal aremaintained for a period of 120 Hz, respectively.
 5. The liquid crystaldisplay according to claim 2, wherein the second flip-flop includes aclock terminal that receives the first period signal, an output terminalthat outputs the second period signal, an inversed output terminal thatoutputs the second inversed period signal, and an input terminal that isconnected to the inversed output terminal.
 6. The liquid crystal displayaccording to claim 5, wherein a high level of the second period signalis maintained for a period of 60 Hz and a low level of the secondinversed period signal is maintained for a period of 60 Hz.
 7. Theliquid crystal display according to claim 2, wherein the first frameinversion polarity signal is a 1 frame inversion polarity signal whichis used at a 1-frame inversion.
 8. The liquid crystal display accordingto claim 2, wherein the second frame inversion polarity signal is a 2frame inversion polarity signal that indicates a 2-frame inversion. 9.The liquid crystal display according to claim 2, wherein the secondframe inversion polarity signal is a 4 frame inversion polarity signalthat indicates a 4-frame inversion.
 10. The liquid crystal displayaccording to claim 2, wherein the second frame inversion polarity signalis an N frame inversion polarity signal that indicates a N-frameinversion, wherein N is an integer which is greater than
 1. 11. Theliquid crystal display according to claim 2, wherein the second frameinversion polarity signal is a Z frame inversion polarity signal thatindicates a Z-frame inversion, wherein Z is an integer which is greaterthan
 2. 12. A liquid crystal display, comprising: a first signalgenerating means that generates a first period signal and a firstinversed period signal in accordance with a gate start pulse; a secondsignal generating means that generates a second period signal and asecond inversed period signal in accordance with the first periodsignal; and a third signal generating means that generates a secondframe inversion polarity signal using the second period signal and thefirst frame inversion polarity signal.
 13. The liquid crystal displayaccording to claim 12, wherein the second signal generating means is aflip-flop having a clock terminal that receives the first period signal,an output terminal that outputs the second period signal, an inversedoutput terminal that outputs the second inversed period signal, and aninput terminal that is connected to the inversed output terminal. 14.The liquid crystal display according to claim 13, wherein a high levelof the second period signal is maintained for a period of 60 Hz and alow level of the second inversed period signal is maintained for aperiod of 60 Hz.
 15. The liquid crystal display according to claim 12,wherein the first signal generating means is a flip-flop having a clockterminal that receives the gate start pulse, an output terminal thatoutputs the first period signal, an inversed output terminal thatoutputs the first inversed period signal, and an input terminal that isconnected to the inversed output terminal.
 16. The liquid crystaldisplay according to claim 15, wherein a high level and a low level ofthe first period signal are maintained for a period of 120 Hz,respectively, and wherein a high level and a low level of the a firstinversed period signal are maintained for a period of 120 Hz,respectively.
 17. The liquid crystal display according to claim 15,wherein the third signal generating means is an exclusive OR gate thatcarries out an exclusive OR logic operation of the second period signaland the first frame inversion polarity signal to generate the secondframe inversion polarity signal.
 18. The liquid crystal displayaccording to claim 17, wherein the first frame inversion polarity signalis a 1 frame inversion polarity signal which is used at a 1-frameinversion.
 19. The liquid crystal display according to claim 17, whereinthe second frame inversion polarity signal is a 2 frame inversionpolarity signal that indicates a 2-frame inversion.
 20. The liquidcrystal display according to claim 17, wherein the second frameinversion polarity signal is a 4 frame inversion polarity signal thatindicates a 4-frame inversion.
 21. The liquid crystal display accordingto claim 17, wherein the second frame inversion polarity signal is an Nframe inversion polarity signal that indicates a N-frame inversion,wherein N is an integer which is greater than
 1. 22. The liquid crystaldisplay according to claim 17, wherein the second frame inversionpolarity signal is a Z frame inversion polarity signal that indicates aZ-frame inversion, wherein Z is an integer which is greater than
 2. 23.A method of driving a liquid crystal display, comprising: generating a 1frame inversion polarity signal which is used at a 1 frame inversion anda gate start pulse that indicates a supply of a scanning pulse;converting the 1 frame inversion polarity signal into a second frameinversion polarity signal in response to the gate start pulse; andchanging the inputted frame to a second frame inversion in response tothe 2 frame inversion polarity signal.
 24. The method of driving theliquid crystal display according to claim 23, wherein a high level and alow level of the first period signal are maintained for a period of 120Hz, respectively, and wherein a high level and a low level of the afirst inversed period signal are maintained for a period of 120 Hz,respectively.
 25. The method of driving the liquid crystal displayaccording to claim 23, wherein a high level of the second period signalis maintained for a period of 60 Hz and a low level of the secondinversed period signal is maintained for a period of 60 Hz.
 26. Themethod of driving the liquid crystal display according to claim 23,wherein the step of converting the 1 frame inversion polarity signalinto the second frame inversion polarity signal includes: generating afirst period signal and a first inversed period signal in accordancewith the gate start pulse; generating a second period signal and asecond inversed period signal in accordance with the first periodsignal; and carrying out an exclusive OR logic operation of the secondperiod signal and the first frame inversion polarity signal to generatethe second frame inversion polarity signal.
 27. The method of drivingthe liquid crystal display according to claim 26, wherein the firstframe inversion polarity signal is a 1 frame inversion polarity signalwhich is used at a 1-frame inversion.
 28. The method of driving theliquid crystal display according to claim 26, wherein the second frameinversion polarity signal is a 2 frame inversion polarity signal thatindicates a 2-frame inversion.
 29. The method of driving the liquidcrystal display according to claim 26, wherein the second frameinversion polarity signal is a 4 frame inversion polarity signal thatindicates a 4-frame inversion.
 30. The method of driving the liquidcrystal display according to claim 26, wherein the second frameinversion polarity signal is an N frame inversion polarity signal thatindicates a N-frame inversion, wherein N is an integer which is greaterthan
 1. 31. The method of driving the liquid crystal display accordingto claim 26, wherein the second frame inversion polarity signal is a Zframe inversion polarity signal that indicates a Z-frame inversion,wherein Z is an integer which is greater than 2.